The invention relates generally to semiconductor circuit memory storage devices and more specifically to the charge storage capability of the capacitors in VLSI memory arrays such as dynamic random access memories (DRAM).
With the advancement of microfabrication technology, semiconductor integrated device density is continuing to increase, and in particular for Dynamic Random Access Memory (DRAM) arrays. In light of the reduction in device dimensions, the charge storage capability of the capacitors in DRAM cells has become an important issue. The minimum requirements for charge storage, charge sensing, and refresh rate for practical memory applications often results in the cell capacitor being one of the largest DRAM circuit components. Thus, the drive to produce higher capacity DRAM circuitry has give risen to much capacitor development. Moreover, the increasing complexity of VLSI fabrication often entails the use of multilayer structures above the silicon substrate. Therefore, electrical and metallurgical properties of multilayer structures have an important effect on the circuit performance and reliability.
A DRAM basically comprises a multiplexed array of charge storage cells, each cell comprising a capacitor connected to an access device such as a field effect transistor. In such designs, the capacitor electrode which is connected to the access device is generally called the xe2x80x9cstorage nodexe2x80x9d or xe2x80x9cstorage polyxe2x80x9d since the material out of which it is formed is often conductively doped polysilicon. The capacitor counter electrode, usually connected to a reference voltage, is called the xe2x80x9ccell plate electrodexe2x80x9d or xe2x80x9ccell poly platexe2x80x9d as it is also often comprised of doped polysilicon. Polysilicon used for capacitor electrodes is typically moderately doped at densities greater than about 1019 cmxe2x88x923 for good conductivity.
In practice, roughened or texturized polysilicon layers are used to increase the effective surface area of the capacitor plates, thereby achieving higher stored charge per unit area of the underlying substrate. To construct such a storage cell, a conductively doped first layer of polysilicon (poly or polycrystalline silicon) is deposited on a wafer. Thereafter, a second polysilicon layer may be deposited and formed into roughened, so-called Hemispherically-Grained Silicon (HGS) thereby forming a capacitor plate having a textured surface morphology. A capacitor dielectric is typically conformally deposited on the HGS poly surface, with the roughened electrode surface providing an enhanced capacitor area. Capacitor dielectrics may for example comprise silicon dioxide or nitride or compositions thereof formed by chemical vapor deposition processes at temperatures ranging from 600xc2x0 C. to 1000xc2x0 C. A subsequent polysilicon deposition on the dielectric film forms the second capacitor electrode.
A common problem associated with the aforementioned capacitor fabrication process is the lack of sufficient out-diffusion of dopants from the doped poly into the HSG during subsequent high temperature processing, resulting in a depletion region adjacent to the cell dielectric. The effect of this depletion region introduces an additional xe2x80x9cdepletionxe2x80x9d capacitance in series with the dielectric capacitance, which causes a substantial reduction in the effective capacitance of the storage capacitor.
Clearly, as the lateral dimensions of DRAM capacitors are reduced, performance must increase to meet minimum charge storage criterion. Thus, there is a clear need in the industry to increase DRAM cell capacitance by reducing the effects of dopant depletion.
One object of the present invention is to provide an integrated circuit capacitor having improved charge storage capability. Increased capacitance is advantageous for applications in capacitor memory arrays such as DRAM arrays. Another object of the present invention is to provide a technique for compensating the effects of depletion in conductively doped polysilicon electrodes, such as used in DRAM storage capacitors.
In accordance with one aspect of the present invention, a capacitor in an integrated circuit comprises an electrode having a fixed or immobile charge density distributed throughout a surface region of the electrode. A dielectric layer is disposed adjacent to the surface region and a second electrode is disposed adjacent to the dielectric layer. The electrodes of the capacitor preferably comprise conductively doped polysilicon and the fixed charge density is preferably incorporated by a plasma nitridation process. Furthermore, the electrodes of such a capacitor preferably have a textured surface morphology and the dielectric layer preferably comprises silicon nitride. The capacitor of the present invention should have a capacitance greater than about 5 fF/xcexcm2, preferably greater than about 10 fF/xcexcm2, and most preferably between about 15 and 80 fF/xcexcm2.
In accordance with another aspect of the present invention, a process for fabricating a capacitor in an integrated circuit comprises the steps of forming a first electrode and then introducing a fixed charge density into a top surface region of the first electrode. The capacitor is then formed by depositing a dielectric layer over and directly contacting the top surface region of the first electrode and then depositing a second electrode over and directly contacting the dielectric layer. The process preferably comprises forming at least the first electrode from conductively doped polysilicon having a textured surface morphology. The fixed charge density is advantageously introduced into the top surface region of the first electrode by a plasma nitridation process followed by a chemical vapor deposited silicon nitride dielectric layer. The second capacitor electrode is also preferably formed by depositing conductively doped polysilicon.
In accordance with yet another aspect of the present invention a method of increasing the capacitance of a capacitor in an integrated circuit comprises forming a first capacitor electrode and subsequently introducing a fixed charge density into a top surface region of the first capacitor electrode. The method further comprises depositing a dielectric layer directly over the top surface region of the first capacitor electrode and subsequently depositing a second capacitor electrode over and directly contacting the dielectric layer. The capacitor electrodes are preferably comprised of conductively doped polysilicon and the fixed charge density is preferably introduced into the first electrode by exposing the top surface region to a plasma comprising ammonia and nitrogen complexes.